WP8.1. Hardware Implementation Optimisation

The objective of this task is to optimise the Hardware Description Language (HDL) of the processing architectures devised in WP6 by enhancing the algorithms parallelism, minimising the memory allocation and improving algorithms locality, thus achieving a suited trade-off between implementation complexity, timing and power consumption. The hardware complexity evaluation will be performed on the basis of state-of-the-art FPGA/DSP boards, and also in view of ASIC implementation and mid and long-term foreseeable HW development.

The hardware emulation will result in the evaluation of the achievable trade-off between computation load, input data rate and computation accuracy. Thus, when a very high input rate is required, high parallel and re-configurable front end processing blocks employing FPGA can be inserted (e.g. demodulation, digital filtering, etc.). However, if input rate complies with DSP capabilities, algorithms can be implemented by multiple DSP processors (see figure below).